This invention is in the field of amplifier circuits, and is more specifically directed to programmable gain amplifiers.
Programmable gain amplifiers, particularly those utilizing operational amplifiers, are well known in the art for providing amplification of analog electrical signals. Those of ordinary skill in the art will recognize that programmable gain amplifiers are particularly useful in the amplification of input signals that may be received over a wide dynamic range; the programmability of the gain of the amplifier permits adjustment of the amplifier operating characteristics according to the amplitude of the input signals being received thereby over time. Additionally, many communications systems are operable according to multiple standards or protocols, such that the specified range and characteristics of the input signals may vary widely among the standards; in such systems, it is useful to have a programmable gain amplifier for receiving and amplifying the input signals, such that the gain of the amplifier may be programmably adjusted according to the desired standard. Also, in many applications such as in the field of analog data communications, programmable gain amplifiers are often used in applying a relatively fine adjustment to incoming signals, prior to such processes as analog-to-digital conversion.
Referring now to FIG. 1, conventional programmable gain amplifier 2 will now be described. In this conventional arrangement, programmable gain amplifier 2 includes operational amplifier 20, which has a non-inverting input connected to ground, and an inverting input that receives an input signal from terminal IN via capacitor 18 and input series resistor RIN. In this conventional arrangement, the output of operational amplifier 20 is presented on terminal OUT, and is also fed back, as negative feedback, to the inverting input via series resistors RA, RB, RC.
According to this conventional arrangement, the programmability of amplifier 2 is effected by metal-oxide-semiconductor (MOS) transistors 22, 24. MOS transistor 22 has its source-drain path connected across resistor RA, while MOS transistor 24 has its source-drain path connected across both of resistors RA, RB; the gates of transistors 22, 24 are controlled by signals at terminals G1, G2, respectively. In this example, a high logic level at terminal G1 (and a low logic level at terminal G2) will cause resistor RA to be shorted out by transistor 22; similarly, a high logic level at terminal G2 will cause both of resistors RA, RB to be shorted out by transistor 24. As is fundamental in the art, the inverting gain of an operational amplifier is proportional to the ratio between the feedback resistance and the input resistance. Accordingly, the feedback resistance of programmable amplifier 2, and thus its gain, is determined by the state of signals G1, G2; in this example, amplifier 2 may have any one of the resistances of RA+RB+RC, RB+RC, or RC as its feedback resistance, depending upon the state of control terminals G1, G2.
It has been observed, according to the present invention, that significant distortion can be produced by amplifier 2 according to this conventional arrangement of FIG. 1. It is contemplated that this distortion is because switching transistors 22, 24, when on, conduct the signal current itself. As illustrated in FIG. 1, when either one of transistors 22 or 24 is turned on, current is conducted therethrough between the input and output terminals IN, OUT, depending upon the signal levels at each (considering that the inverting input of operational amplifier 20 typically has an extremely high input impedance). Because the source-drain resistance of an MOS transistor depends upon the current conducted therethrough, the feedback resistance presented by the ones of series resistors RB, RC not shorted out plus the source-drain resistance of the shorting transistor 22, 24 will vary with signal current. Particularly in high precision applications such as high frequency modems, this distortion in programmable gain amplifiers such as amplifier 2 may not be tolerable.
FIG. 2 illustrates another conventional programmable gain amplifier 25, in which the distortion due to signal current being conducted by the shorting transistors of the example of FIG. 1 is avoided. In this example, input line IN is capacitively coupled to an integrated circuit containing programmable gain amplifier 25 via external high-pass coupling capacitor 18 connected to bond pad BP of the integrated circuit (boundary B of FIG. 2 illustrating the chip boundary of the integrated circuit). Programmable gain amplifier 25 has its gain programmably set through operation of switches S12, S23, S3X, which are connected between the inverting input of operational amplifier 30 and nodes between resistors R1, R2, R3, RX, which are connected in series between the output of amplifier 30 and external coupling capacitor 18. The values of resistors R1, R2, R3, RX will typically vary among themselves, depending upon the range and resolution of programmable gain levels desired for amplifier 25. The non-inverting input of amplifier 30 is biased to ground, and the output of amplifier 30 is presented at terminal OUT.
Similarly as in the case described above relative to FIG. 1, switches S12, S23, S3X are generally implemented by way of MOS transistors, with a control signal connected to the gate of each that sets the state of each switch S12, S23, S3X. The state of switches S12, S23, S3X determine the gain of programmable gain amplifier 25, by setting the ratio between feedback and input resistance as seen by amplifier 30. As noted above, the gain of amplifier 25 is proportional to the ratio between its feedback resistance and its input resistance. For example, if switch S23 is closed and all other switches S12, S3X are open, the gain of programmable gain amplifier 25 will be proportional to             RX      +      R3              R1      +      R2        .
Other combinations of switches S12, S23, S3X will select different ratios of feedback to input resistance and thus implement a different gain.
Programmable gain amplifier 25 of FIG 2 avoids one type of distortion, namely that caused by the switching transistors conducting signal current as in the case described above relative to FIG. 1. This is because one may safely consider the inverting input of operational amplifier 30 as having extremely high impedance. The high input impedance of operational amplifier 30 limits the current that must be conducted by any one of switches S12, S23, S3X, implemented as MOS transistors, as switches S12, S23, S3X are connected between the inverting input of operational amplifier 30 and a node along the resistor chain of the input and feedback resistors. As such, signal current is never conducted by switches S12, S23, S3X, and thus no current-dependent changes are presented thereby. As such, the low frequency behavior of programmable gain amplifier 25 is of quite high fidelity.
However, changes in the gain of programmable gain amplifier 25 will also change its high frequency response. Specifically, the high-pass filter established by external capacitor 18 of capacitance C18 will have a pole determined by       1                  R        in            ⁢              C        18              ,
where Rin is the input resistance. These changes in high frequency response will thus modulate the frequency response of the overall circuit from the ideal, causing distortion in the amplified signal at terminal OUT. As discussed above, especially in high precision communications applications such as high data rate modems, distortion due to programmable gain amplifiers is quite undesirable. Indeed, this conventional programmable gain amplifier 25 of FIG. 2 requires adjustment in the input signal level presented thereto according to the selected gain in order to avoid this high frequency distortion.
It is therefore an object of the present invention to provide a programmable gain amplifier having reduced high frequency distortion.
It is a further object of the present invention to provide such a programmable gain amplifier in which the input impedance presented thereby is constant over variations in the gain of the amplifier.
It is a further object of the present invention to provide such a programmable gain amplifier in which the input signal level need not be adjusted according to the programmed gain.
It is a further object of the present invention to provide such a programmable gain amplifier that may be efficiently implemented into an integrated circuit.
It is a further object of the present invention to provide such a programmable gain amplifier that may be efficiently implemented into analog front end functionality in a DSL modem system.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented into a programmable gain amplifier, such as may be implemented into an analog front end integrated circuit for digital subscriber line (DSL) modems. According to the present invention, the programmable gain amplifier includes a series of resistors connected between the output of an operational amplifier and an input terminal, with switches in a first set provided to selectably connect one of several taps along the resistor series to an amplifier input. Additionally, a series of resistors is connected between the amplifier input and ground, with switches connected to taps along this series, to short out one or more of the resistors in the series in a manner corresponding to the gain selected by the first set of switches. As a result, a parallel matching resistance is varied with the selected gain of the programmable gain amplifier, stabilizing the high frequency operation of the circuit.